A methodology is proposed for the design of a 4-Bit Arithmetic Logic Unit (ALU) based on Soft-Hardware-Logic (SHL). The core of the implementation is based on the device known as neu-MOS (ν-MOS), a floating-gate MOS transistor with more than one control gate used for the digital signal processing. This configuration is reconfigurable modifying only the external voltages applied to an intermediate stage of programmable CMOS inverters, without any circuitry change, in contrast with conventional digital implementations. Here it is demonstrated that using a universal circuit, basic Boolean functions like AND, NAND, OR, NOR, Exclusive-OR and Exclusive-NOR can be configured using Multiple-Input Floating-Gate (MIFG) Transistors or neu-MOS. Based on a graphical method called Floating-gate Potential Diagram (FPD), a very basic 4-Bit ALU was designed and simulated for a couple of arithmetic and logic functions taking advantage of the weighted sum performed at the floating gate of the neu-MOS. Weighted inputs can be obtained from the FPD and then converted to effective capacitances choosing a given CMOS technology, OnSemi's 0.5 μm technology, for instance. Results obtained from simulations of the proposed design are compared with experimental results of ALUs configured with a FPGA evaluation kit and Motorola's MC14581B ALU chip.
DOI: https://doi.org/10.1109/iceee.2012.6421136
Publish Year: 2012
